1. Field of the Invention
The present invention relates to a coreless substrate having filled via pads and a method of manufacturing the same, and more particularly to a coreless substrate having filled via pads in which a filled via having the same height as that of an insulating layer is used as a pad and a method of manufacturing the same.
2. Description of the Related Art
These days, with developments in the electronics industry, demands for the miniaturization and increased functionality of electronic components have rapidly increased, and printed circuit boards incorporating such electronic components therein also are requiring high density circuit and thin substrates.
In particular, a typical build-up printed circuit board is manufactured in a manner such that a build-up layer is formed on a core substrate, and thus the resulting build-up printed circuit board product still containing the core substrate therein is used. Unfortunately, this causes an increase in the total thickness of the printed circuit board. If a thickness of the printed circuit board increases, the length of the circuit is elongated, and thus an increased amount of time is required for signal processing.
To solve the above problems, a coreless substrate rather than a core substrate having a thick thickness has been proposed. FIGS. 1 to 5 show a process of manufacturing the conventional coreless substrate.
Hereinafter, a process of manufacturing the conventional coreless substrate is described with reference to FIGS. 1 to 5.
As shown in FIG. 1, a lower insulating layer 12 is first formed on a metal carrier 11 for supporting a coreless substrate.
As shown in FIG. 2, a build-up layer 13, which includes a circuit layer 13b composed of a plurality of build-up insulating layers 13a and a plurality of circuit layers 13b having vias 13c, is formed on the lower insulating layer 12, and an upper insulating layer 14 is formed on the build-up layer 13.
Subsequently, as shown in FIG. 3, upper openings 14a are formed in the upper insulating layer 14 such that upper pads of the uppermost circuit layer 13b contained in the build-up layer 13 are exposed through the upper openings 14a. In this process, the openings 14a may be formed using a drilling machining or a laser radiation.
As shown in FIG. 4, the metal carrier 11 is eliminated using etching.
Finally, as shown in FIG. 5, lower openings 12a are formed in the lower insulating layer 12 such that lower pads of the lowermost circuit layer 13b contained in the build-up layer 13 are exposed through the lower openings 12a, and then solder balls 15 are formed on the upper and lower pads for the connection with exterior connecting terminals.
Through the above-described process, the conventional coreless substrate 10 is manufactured.
However, the conventional coreless substrate 10 and the method of manufacturing the coreless substrate have the following disadvantages.
First, since the conventional coreless substrate 10 is configured such that the upper and lower pads are exposed through the upper openings 14a and the lower openings 12a, respectively, as shown in FIG. 5, the coreless substrate may have stepped portions which deteriorate matching accuracy between the solder balls 15 and the upper/lower pads and also deteriorate the reliability of bonding.
Furthermore, since the conventional method of manufacturing a coreless substrate 10 involves the use of a metal carrier 11 to support the coreless substrate 10 during the manufacturing process, manufacturing costs are increased. In addition to this, since the method involves an etching process of eliminating the metal carrier 11, manufacturing time is increased.
Also, since the build-up layer 13 is provided only at one side with respect to the metal carrier 11, productivity thereof is decreased. In addition, when the process of forming the build-up layer is conducted only at one side, products become seriously warped during the manufacturing process.
In addition, during drilling or laser machining when forming the upper openings 14a and the lower openings 12a in the upper insulating layer 14 and the lower insulating layer 12 so as to expose the upper and lower pads through the upper and lower openings, the coreless substrate 10 become warped, and stepped portions are inevitably generated between the pads and the openings 12a and 14a due to the thicknesses of the upper insulating layer 14 and the lower insulating layer 12.
Furthermore, when the metal mask and the thin coreless substrate 10 are bonded to each other in the screen printing process of forming solder balls or bumps for connecting the coreless substrate 10 with an electronic component, a clearance occurs therebetween, thus hindering an even application of solder onto the coreless substrate 10. Because of the above problems, uniformities of heights and diameters of solder balls or bumps are decreased in the reflow and coining processes, thus decreasing the production yield.